新型埋入式板级封装技术

Abstract

Consumer and enterprise applications have precipitated an insatiable appetite for ever-increasing density, functionality, and portability requirements of active devices. Such aggressive requirements, which have challenged the viability of conventional packaging technologies, have prompted researchers and engineers to explore suitable alternatives. Garnering the attention of academia and industry is Embedded Panel Level Package. This enabling technology significantly enhances the versatility of the overall package thereby facilitating contemporary density and functionality requirements. A viable process to enable Embedded Panel Level Package would finally permit designers to incorporate all components on and inside the substrate, thus entailing a 3-D System-in-Package (SiP). In this paper, we illustrate the design, fabrication and testing of embedded MOSFET dies to exemplify the viability of this emerging technology. The impetus of this heuristic study is to develop a practical solution that is conducive to reduced manufacturing costs and truncated time-to-market product development cycles. Thus, we propose a streamlined methodology involving the simulation, optimization and fabrication of active chips embedded in organic substrates by employing a novel hybrid manufacturing process. Emphasis is placed on the simulation of thermal loading conditions and thermal-mechanical properties. It is imperative to incorporate sufficient thermal margins to ensure the viability of the fabricated embedded devices. Optimized thermal-loading and thermal-mechanical designs of the embedded MOSFET die are efficiently facilitated by numerical simulations based on finite element analyses (FEA). Finally, resistance and functional tests of the fabricated embedded MOSFET have been performed thereby demonstrating the viability of the manufacturing process for embedding active devices.