高速脉冲超宽带系统和芯片设计

Abstract

Impulse radio (IR) ultra-wideband (UWB) wireless communication system has the advantages of low power consumption and low complexity. However, its transmission rate is usually limited. This paper proposes a high-speed IR-UWB system scheme. By using high sampling rate, low resolution quantization, and digital processing, the proposed scheme achieves more than 100 Mbps wireless transmission rate with reasonable power consumption and complexity. The system scheme, core algorithms, key implementations in the chip design, and simulation results are given in the paper. As a core algorithm, a joint synchronization and channel estimation (JSCE) algorithm is proposed. The JSCE algorithm conducts synchronization and channel estimation at the same time. It has the advantage of low complexity and is feasible to real-time implementation. The implementation issues in the chip design, including the digital baseband chip structure, the state transform of the receiver, and the implementation of the JSCE algorithm are introduced. Based on the proposed system scheme, a digital baseband chip is designed and fabricated. The core power consumption of the chip is less than 100 mW. An experimental system is also implemented which uses the baseband chip as a core processor. The system is capable of real-time high de nition video transmission. Experimental results on the experimental system validate the proposed system scheme.