Abstract
A method of direct memory access subsystem verification used for “Elbrus” series microprocessors has been described. A peripheral controller imitator has been developed in order to reduce verification overhead. The model of imitator has been included into the functional machine simulator. A pseudorandom test generator for verification of the direct memory access subsystem has been based on the simulator.
Highlights
Modern computer systems require very intensive data exchange between the peripheral devices and the random-access memory
This article is based on a result of a comprehensive project than combined implementation of a three co-designed verification techniques based on the consecutive investigation of the direct memory access (DMA) subsystem employing one the three models: 1) a functional model written in C++ that corresponds to behavior of the subsystem in the environment determined by a real computer system configuration, 2) RTL model in Verilog and 3) FPGA-based prototype
Employment of the test generator built using the approach described in this paper allowed to find 45 bugs in three different “Elbrus” series microprocessors: 24 in a single-cores low-power CPU and no cache coherence support, 16 in a eight-core CPU supporting up to 32 core per ccNUMA system with coherent DMA and 5 in the generation eightcore CPU with ccNUMA and updated coherence protocol
Summary
Modern computer systems require very intensive data exchange between the peripheral devices and the random-access memory. The most important problem that significantly affects the quality of the subsystem verification is the exhaustiveness of the representation of the external devices connected to it and input vectors they generate. In this case, the problem has been. 139-148 solved by introducing a device imitating a peripheral controller and capable of generating a comprehensive range of DMA subsystem interaction patterns into the functional model. The exhaustiveness of the subsystem in question verification is achieved with a test generator allowing to provide necessary inputs using the imitator. A functional model library that will be described in the third section has been reused from previous projects in order to fulfill this requirement
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