Multi-Vt Performance Dependence on Capping Layer Position by NPT for PMOS Device Applications

Abstract

In this paper, we present the comprehensive investigation of multi-Vt performance dependence on ALD-TiN capping layer position by NPT (nitrogen plasma treatment) process. The basic performance of fabricated PMOSCAPs are strongly dependent on the capping layer position by NPT process. 1) Flat-band voltage (VFB) negative shift is suppressed by increasing capping layer thickness before NPT process and EWF is toward band edge for the low power PMOS application, compared to the direct NPT at high-k surface. 2) Without capping layer shielding, the direct NPT process at HfO2 (high-k) surface brings out the oxygen vacancy generation and metal gate fermi level pinning and EWF toward band center for high performance PMOS application, while the capping layer can shield the nitrogen plasma with improvement of equivalent oxide thickness (EOT) and bulk trap density (Not). 3) The interface trap density (Dit) by conductance method is found to be significantly reduced by 35% compared to NPT process applied at capping layer top position. 4) The unique charge neutrality and oxygen vacancy model incorporating with capping layer shielding is reasonably proposed and successfully explains the above multi-Vt performance dependence on NPT position. The investigation of multi-Vt performance on capping layer position dependence by NPT will encourage the process improvement and advance HKMG technology for PMOS device multi-applications.