Multi-terminal-net river routing for VLSI layout design

Abstract

Consideration is given to the single layer rectilinear river routing of n nets and the two sets of terminals (of the nets) which lie on two horizontal lines are connected by means of disjoint wires on a unit-grid (where one unit is the minimum spacing between two wires). A wire realizing a net will connect all the consecutive terminals of the net on the top line to all the consecutive terminals of the net on the bottom line and there are at most J horizontal segments (jogs) in the wire. For J=1, a linear time algorithm for finding a layout with the minimum distance (separation) between the two horizontal lines is given. When sliding the upper horizontal line is allowed, the authors show a linear time algorithm for finding all possible sliding offsets to achieve an s-separation layout. In addition, an O(n log n) time algorithm for finding an offset which yields the smallest possible separation is provided. Given J>1 and an offset, the authors show an O(Jn) time algorithm for determining if an s-separation is feasible, and an O(Jn log n) time algorithm for finding a layout with the minimum separation. >