Multi-State 2-Bit CMOS Logic Using n- and p- Quantum Well Channel Spatial Wavefunction Switched (SWS) FETs

Abstract

Unlike conventional FETs, spatial wavefunction switched (SWS)-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The aim of this paper is to present 4-states/2-bit output-input transfer characteristics using two Si/SiGe quantum well channels configured as CMOS using n- and p-channel spatial wavefunction switched field-effect transistors (SWS-FETs). Quantum simulations show switching of wavefunctions as the gate voltage is increased from lower Si quantum well to the upper well in n-channel and from upper SiGe quantum well to lower well in the p-channel. The inverter transfer characteristic and current switching are obtained by integrating BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). The simulation shows current flow only during switching.