Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface

Abstract

In this work, a multi-slew-rate output driver is developed to cope with the supply voltage variation and the different I/O component capacitance (denoted by CIO) condition. For accurate data transfer, it is necessary to reduce the design loss in the impedance-calibration circuit and to minimize CIO in the coded output driver. With these methods, a data rate of 3 Gb/s/pin is achieved and the shmoo plot. The micrograph of the output driver and impedance calibration circuit, which is implemented in a 66 nm 512 Mb GDDR3 SDRAM.