Multiscale modeling of defect-related phenomena in high-k based logic and memory devices

Abstract

We present a multiscale modeling platform that exploits ab-initio calculation results and a material-related description of the most relevant defect-related phenomena in dielectrics (charge trapping and transport, degradation and atomic species motion) to interpret the reliability and electrical characteristics of logic and memory devices. The model is used to identify and characterize the dielectric defects responsible for the charge transport and degradation in SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /high-k (HK) bi-layer logic devices and to investigate the kinetics of forming and switching operations of Hf-based RRAM memories. Simulation results provide a deep and quantitative understanding of the factors controlling device operation and reliability. The proposed multiscale modeling platform represents a powerful tool for investigating material properties and optimizing device performances and reliability.