Abstract

The dimensions of microbumps in three-dimensional integration reach microscopic scales and thus necessitate a study of the multiscale microstructures in microbumps. Here, we present simulated mesoscale and atomic-scale microstructures of microbumps using phase field and phase field crystal models. Coupled microstructure, mechanical stress, and electromigration modeling was performed to highlight the microstructural effects on the reliability of microbumps. The results suggest that the size and geometry of microbumps can influence both the mesoscale and atomic-scale microstructural formation during solidification. An external stress imposed on the microbump can cause ordered phase growth along the boundaries of the microbump. Mesoscale microstructures formed in the microbumps from solidification, solid state phase separation, and coarsening processes suggest that the microstructures in smaller microbumps are more heterogeneous. Due to the differences in microstructures, the von Mises stress distributions in microbumps of different sizes and geometries vary. In addition, a combined effect resulting from the connectivity of the phase morphology and the amount of interface present in the mesoscale microstructure can influence the electromigration reliability of microbumps.

Highlights

  • Three-dimensional (3D) integration is an emerging technology in which multiple materials, technologies, and functional components are vertically stacked and interconnected to form highly integrated micro-nano systems [1]

  • This study aims to systematically investigate multiscale microstructural formation and subsequent microstructural effects on the reliability of microbumps for 3D integration using a modeling and simulation approach

  • A phase field model introduced by Kim et al [20] is used to simulate the microstructural evolution during solidification within one half of the cross-section of a microbump

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Summary

Introduction

Three-dimensional (3D) integration is an emerging technology in which multiple materials, technologies, and functional components are vertically stacked and interconnected to form highly integrated micro-nano systems [1]. Three dimensional integration technology has the potential to increase system performance in many applications, from mobile to high-performance computing and high density memories. Techniques such as through-silicon-via (TSV) and fine-pitch bumping allow for a dense integration of heterogeneous technologies. As complementary metal oxide semiconductor (CMOS) technology barely provides the expected performance improvement, this dense integration of heterogeneous technologies is critical in maintaining Moore’s momentum [2,3,4,5,6,7]. Electromigration reliability requires improved interface control; dielectric reliability depends on the barrier-/low-k and chemical mechanical polishing (CMP)-interface control. Stress-induced voiding is driven by stress gradients, and chip-package interactions are increasingly difficult to minimize when porous dielectrics with a low Young’s modulus are used [2]

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