Multirate ΣΔ modulators

Abstract

New high-speed /spl Sigma//spl Delta/ analog to digital converters (ADCs) are required for xDSL and RF receivers. As sampling frequency is upper limited by the amplifier bandwidth and power consumption, these high-speed, low-power converters operate with a small oversampling ratio. Usually, they are high-order cascade structures with a multibit quantizer in the last stage. All these approaches use a unique sampling frequency. This paper shows that multirating is a useful technique to reduce power consumption in high speed /spl Sigma//spl Delta/ modulators. To this end, two different multirate /spl Sigma//spl Delta/ modulators are proposed. The first one uses a low sampling frequency in the first integrator(s) of a single loop structure, while the second one uses a low oversampling frequency in the first stage(s) of a cascade converter.