Multiprocessor system on chip with shared memory using crossbar topology

Abstract

Multiprocessor system on chip offers a set of processors, embedded in one single chip. A parallel application can, then, be scheduled to each processor, in order to accelerate its execution, using either shared memory or message passing for exchanging data. In this case, the use of a shared bus is no longer a viable solution, due to its high contention. In order to allow for non-blocking parallelism, we implemented the interconnection network based on the crossbar topology. In this kind of interconnection, processors have full access to their own memory module simultaneously, besides been able to address the whole memory. One processor accesses the memory module of another processor only when it needs to retrieve data generated by the latter. This paper presents the specification and modelling of an interconnection network based on the crossbar topology. The aim of this work is to investigate the performance characteristics of a parallel application running on this platform.