Multiprocessor implementation models for adaptive algorithms

Abstract

This paper addresses the problem of implementing adaptive algorithms on parallel MIMD message-passing computers using a small number of digital signal processors. First, we evaluate the maximal speedup obtained by an ideal machine without resources restriction but taking into account interprocessor communications. This estimation is based on the signal flow graph of the algorithm and a description of the parameters of the target architecture. Explicit expressions are obtained and critical tasks are detected, thus allowing a fast and easy evaluation of the influence of implementation parameters. Next, we propose some techniques to enhance the intrinsic parallelism of iterative algorithms using our models. An algorithm is given to find an implementation achieving maximal speedup and using a small number of processors. Then, an optimal intercommunication network is obtained and some techniques are given to reduce the number of point-to-point links between processors without affecting the speedup. Finally, if the optimal network cannot be constructed because of an excessive number of links, we propose an allocation method to minimize the performance degradation introduced by the use of a fixed arbitrary communication network.