Multi-port high bandwidth interconnect equivalent circuit model for 3.2 Gbps channel simulation

Abstract

S-parameter is commonly used for channel modeling and crosstalk modeling between channels in high speed digital design. However, for I/O buffer circuit designer, S-parameter models are not well received owing to all general frequency domain data is difficult to incorporate into a transient circuit simulation. S-parameter is a frequency domain data and is difficult to deal in a transient circuit simulation especially when S-parameter is broadband with multi-port as well as causality and passivity issues exist. Hence, Spice model or Spice-equivalent model is needed for transient circuit simulation. A lumped-elements Spice model only allows circuit designers to perform accurate simulation at lower data rate. In high speed design, lumped-elements Spice model does not provide sufficient bandwidth for accurate transient simulation analysis. Therefore, there is a need to create high bandwidth Spice model with sufficient bandwidth to support accurate channel transient circuit simulation. This paper discusses the creation of high channel count package equivalent circuit models for channel timing analysis in 3.2Gbps range. It highlights the challenges in developing the methodology to accurately deliver a high channel count and high bandwidth Spice-equivalent sub-circuit models which is compatible with Spice-based circuit simulator. The modeling methodology improves simulation run time and preserving passivity as well as the causality of the compact circuit model while maintaining the original S-parameter behavioral model. The proposed high bandwidth model offers dramatically faster simulation time without sacrificing accuracy. The resultant of this study will allow more aggressive and accurate signal integrity analysis.