Multiplierless chaotic Pseudo random number generators

Abstract

This paper presents a multiplierless based FPGA implementation for six different chaotic Pseudo Random Number Generators (PRNGs) that are based on: Chua, modified Lorenz, modified Rössler, Frequency Dependent Negative Resistor (FDNR) oscillator, and other two systems that are modelled using the simple jerk equation. These chosen systems can be employed in high speed applications because they don’t utilize any hardware multiplier. The proposed PRNGs have been implemented using VHDL, synthesized on Xilinx, using the FPGA: XC5VLX50T, and tested using the NIST statistical suite. Furthermore, a comparison has been established between the performance of all the PRNGs, regarding the implementation area, speed, and the statistical randomness quality. It has been found that the modified Lorenz PRNG has the best randomness quality and the best hardware performance as it can pass all the NIST tests while operating at 298.597 MHz and utilizing only 0.23% and 0.62% from the FPGA’s slice registers and Look-Up-Tables (LUTs) respectively.