Abstract
In this paper, the periodically time-varying (PTV) structure, previously proposed for realizing FIR filters, is extended to IIR filter realization. The realization consists of ternary ({0, ±1}) or quinary ({0, ±1, ±2}) PTV coefficients with simple input and output units. Coefficient multiplications as well as the input and output units require no hardware multiplier, which helps increase the processing speed or reduce the chip area. Bit-level architectures are presented. The regularity and local interconnection of the architectures help simplify VLSI design and layout.
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