Multiplexer Based Error Efficient Fixed-Width Adder Tree Design for Signal Processing Applications

Abstract

BACKGROUND: In copious mixed media applications, humans cannot necessarily discern error free or erroneous outputs, owing to the small range of perception abilities. Crucial information can still be obtained from marginally inexact outputs. Leveraging this, many algorithms such as Digital Signal Processing (DSP), Discrete Cosine Transform (DCT), Motion Compensation (MC) use approximate calculations while still maintaining appreciable computation accuracy. METHOD: When data processing algorithms are taken into consideration, adders play an important role in the arithmetic module by managing the power and area utilization of the system. A fixed-width adder tree design for approximate calculations is proposed, that uses the trade-off between area and accuracy as the base for analysis. Our design uses 12.42%, 18.17% and 5.05% lesser area compared to the full width adder tree, FX- AT-PT and FX-AT-DT respectively. Additionally, when compared to FX-AT-DT, TFX-AT and ITFX-AT, the proposed design has an RESULT: To cope with the inaccuracy caused by truncation, the proposed design employs mux-based radix-4 addition coupled with bias estimation. Further, to examine the error performance we have incorporated the proposed design and a few other existing designs into the Walsh-Hadamard Transform (WHT), to process images with different metrics and compare the Peak Signal to Noise Ratio (PSNR) of the images. CONCLUSION: It was observed that the proposed design showed significant improvement in the PSNR score when compared to ITFX-AT and maintains a score similar to that of FX-AT-PT.