Multiple-Valued Logic Gates Using Asymmetric Single-Electron Transistors

Abstract

This paper proposes novel multiple-valued (MV) logic gates by using asymmetric single-electron transistors (SETs). Asymmetric single-electron transistors have two tunneling junctions with largely different resistances and capacitances. We fully exploited the unique Coulomb staircase characteristic of asymmetric SETs to compactly finish logic operations. We build MV literal gates with wide range of radixes by using a pair of asymmetric SETs. We showed that, arbitrary radix-4 literal gate can be realized using a pair of asymmetric SETs. We also proposed MV analog-digital conversion circuits. The MV logic gates have very compact structures and low power dissipation.