Multiple-parameter CMOS IC testing with increased sensitivity for I/sub DDQ/

Abstract

Technology scaling challenges the effectiveness of current-based test techniques such as I/sub DDQ/. Furthermore, existing leakage reduction techniques are not as effective in aggressively scaled technologies. We exploited intrinsic dependencies of transistor and circuit leakage on clock frequency, temperature, and reverse body bias (RBB) to discriminate fast ICs from defective ones. Transistor and circuit parameters were measured and correlated to demonstrate leakage-based testing solutions with improved sensitivity. We used a test IC with available body terminals for our experimental measurements. Our data suggest adopting a sensitive multiple-parameter test solution. For high performance IC applications, we propose a new test technique, I/sub DDQ/ versus F/sub MAX/ (maximum operating frequency), in conjunction with using temperature (or RBB) to improve the defect detection sensitivity. For cost sensitive applications, I/sub DDQ/ versus temperature test can be deployed. Our data show that temperature (cooling from 110/spl deg/C to room) improved sensitivity of I/sub DDQ/ versus F/sub MAX/ two-parameter test by more than an order of magnitude (13.8/spl times/). The sensitivity can also be tuned by proper selection of a temperature range to match a required defect per million (DPM) level.