Abstract
Estimating relative camera pose is the key problem of visual odometry (VO). To achieve better efficiency, sparse key-points are usually relied on for the estimation. Yet, feature extraction and matching are still computationally demanding, hindering the overall VO from real-time processing. Exploiting the superiorities of an FPGA in terms of high efficiency, low power consumption, and low cost, this paper proposes a multiple master-slave FPGA architecture for an SIFT-based stereo VO. The master-slave design enables high reconfiguration for the data throughputs among various modules. These modules include SIFT, matching, pose estimation, and their corresponding controllers. In the SIFT module, hardware implemented image pyramid is proposed, where scales are determined off-line via a minimization approach. Local linear exhausted search (LES) matching is considered for both the stereo and the frame matching. In the pose estimation module, a novel hardware design of deriving closest orthogonal matrix for 3D-3D correspondences of relative pose estimation is proposed. Experimental results show that 33.2 fps can be achieved using KITTI dataset without the need of a large number of hardware resources. The proposed reconfigurable design also facilitates its expansions of adopting CCD cameras as well as developing SLAM and other applications.
Highlights
Characterized by low cost, low power consumption and rich information, cameras are becoming the highly interested sensors for many visual autonomous systems
The results show that Field Programmable Gate Arrays (FPGA) obviously surpassed other computing platforms
Time-costly feature extraction and matching was accelerated by an FPGA, while an ARM software was in responsible for the floating point arithmetic computation required in pose estimation
Summary
Characterized by low cost, low power consumption and rich information, cameras are becoming the highly interested sensors for many visual autonomous systems. Another work [14] named Navion was proposed to provide a fully integrated stereo non-filtering based VIO system on an ASIC using lightweight Shi-Tomasi corners It incorporates a graph optimization backend to regularize both poses and 3D features. Shi-Tomasi corners were extracted as features in the system, and ARM software was introduced to obtain optimal parameters for the algorithm prior to developing a fully integrated chip Time-costly feature extraction and matching was accelerated by an FPGA, while an ARM software was in responsible for the floating point arithmetic computation required in pose estimation. SIFT feature extraction, matching, and pose estimation are achieved by hardware, whereas an Altera’s Intel soft core Nios II is only responsible for managing data transfer between hardware modules and off-chip memories.
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