Abstract
Simulators are generally used during the design of computer architectures. Typically, different simulators with different levels of complexity, speed and accuracy are used. However, for early design space exploration, simulators with less complexity, high simulation speed and reasonable accuracy are desired. It is also required that these simulators have a short development time and that changes in the design require less effort in the implementation in order to perform experiments and see the effects of changes in the design. These simulators are termed high-level simulators in the context of computer architecture. In this paper, we present multiple levels of abstractions in a high-level simulation of a general-purpose many-core system, where the objective of every level is to improve the accuracy in simulation without significantly affecting the complexity and simulation speed.
Highlights
With the current trend of many-core systems, we interpret Moore’s law as the number of cores will be doubled every new generation of processor
Once we have found that particular window size, we can use this during the execution of the program leaving space for other threads required by a different applications, in the case of application implementation or, in the case of chip design, determine the maximum limit across the range of target applications and use this to limit the thread table structure and register file size
Simulations are commonly used during the design of computer architectures
Summary
With the current trend of many-core systems, we interpret Moore’s law as the number of cores will be doubled every new generation of processor. The suggested concurrent programming model for this chip is based on fork-join constructs, where each created thread can define further concurrency hierarchically This model is called the microthreading model and is applicable to current multi-core architectures using a library of the concurrency constructs called svp-ptl [6] built on top of pthreads. Each core implements the concurrency constructs in its instruction set and is able to support hundreds of threads and their contexts, called microthreads and tens of families (i.e. ordered collections of identical microthreads) simultaneously. This implementation is referred as the Microgrid.
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