Multiple-input and -output OR/AND circuits for VLSI GaAs IC's

Abstract

OR/AND circuits with multiple input and output have been demonstrated experimentally for low-power 2K and 6K GaAs gate arrays with two levels of logic at approximately a 155-percent increase in speed and power product. The proposed multiple-logic levels process in parallel some complex logic functions with only one gate delay. Two proposed bootstrap techniques have shown an improvement of typically 12 percent in speed without an increase in power for low-power applications. In coupling these OR/AND circuits with the allowable buffered stage and the bootstrap enhancements, one can obtain good device performance over a spectrum of SSI to VLSI in the SDFL circuit family.