Abstract
Planar single-gate transistors have been recently demonstrated with reasonable performance at sub-20 nm of physical gate length. However, a need for high performance transistors with channels shorter than that, as expressed by 2005 ITRS goals, requires devices with more than one gate, which facilitates better control of electrostatic charge in the channel. Double- and triple-gate transistors with their process integration complexity will likely become a device of choice for the high performance logic circuits in second decade of the 21st century. This paper will discuss various approaches to realization of those multi-gate fully depleted channel devices and their performance and process integration issues and layout design challenges for sub-20 nm gates. We also discuss issues related to designing circuits with multi-gate fin-based devices.
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