Multiple Fault Detection in Nano Programmable Logic Arrays

Abstract

This paper presents a new method for testing on a go-nogo basis nano programmable logic arrays; the basic configuration of an array made of passive and active interconnect resources (lines and switches) on two connected planes (AND and OR) is analyzed under a comprehensive multiple fault model. This model is applicable to production testing at nano manufacturing and considers faults (such as stuck-at and bridging faults) in the passive interconnect line structure as well as programming faults in the active resources (switching or crosspoint faults). The proposed method achieves full coverage in fault detection by configuring the array multiple times using a four-step procedure; as the complexity of testing such chip is largely dependent on the number of configuration rounds (also often referred to as programming phases) that the chip must undergo, then at production the proposed method achieves a substantial reduction in test time compared with previous techniques. Different from previous techniques that have a complexity as function of array size (i.e. quadratic with the dimension of the planes in the array), it is shown that the proposed technique has a complexity linear with the largest dimension of a plane in the nano array. Simulation results are provided to show that 100% detection is achieved and for detection, the average number of configuration rounds is significantly less than the upper bound predicted by the presented theory.