Abstract
A method for analyzing multiple faults in gate-level combinational circuits that does not explicitly enumerate all the multiple stuck-at faults that may be present in a circuit is presented. First, a fault collapsing phase is applied to the network, so that equivalent faults are eliminated. During the analysis, frontier faults where there is at least a normal path from each faulty line to a primary output are considered. It is shown that the set of frontier faults is equivalent to the set of multiple faults. Given an input vector, the normal circuit is evaluated and the fault effects propagated. A fault dropping procedure is then applied to eliminate faulty conditions on specific lines that are either absent or permanently masked by other faulty conditions. The method is applied to some benchmark circuits, and significant speedup is observed. >
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