Abstract

Finite Impulse Response (FIR) filters are the most important elements in digital signal processing that are packed with dedicated hardware instead of software to improve the speed. Implement the reconfigurable filter architectures to obtain a low power, high speed implementation of variable size partitioning FIR filter. By using the Multiple Constant Multiplication (MCM) technique the computationally efficient low power, high speed RADIX-2^r variable size FIR filter would be designed. To realize both low pass and high pass filter, module based dynamic partial reconfiguration is proposed and it also reduce the reconfiguration time. The FIR filters are designed using the tool Xilinx13.2. Filters are dynamically reconfigured by modifying the filter’s coefficients.

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