Abstract
This paper presents a technique for minimizing the test-application time of a circuit board designed with boundary scan. The technique is based on the use of multiple boundary scan paths. The paper discusses how the boundary scan paths are selected and provides analytical expressions for comparing test-application times for different boundary scan configurations on a circuit board. The paper shows that for certain circuit board configurations the use of multiple boundary scan paths can result to significant reduction in test application time at the expense of a few additional board I/O.
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