Multiple bit upset correction in SRAM based FPGA using Mutation and Erasure codes

Abstract

SRAM based FPGAs that are based on a nanometer technology with denser integration schemes are used most widely now-a-days. When the radiation in the environment strikes any one of the configuration frames, it would seriously affect the functionality of the SRAM based FPGA which leads to Multiple Bit Upsets (MBUs). These MBUs affect a larger number of configuration frames in SRAM based FPGA. So in order to rebuild the incorrect configuration frames, a lower cost error-correction code is used for the correction and detection of MBUs in configuration frames founded on the conception of Erasure codes. Horizontal and Vertical parity bits has been used to evade redundant data. The proposed scheme does not require any alteration to the FPGA architecture. The only drawback is that, parity bit operation is performed for all the configuration frames even when Single Event Upset is occurred which increases computation time. In order to overcome this drawback, Mutation along with cross over is utilized which is used to correct the single bit errors. Erroneous frames could be corrected from the golden memory reference module. By using the Erasure or Mutation the delay is reduced furtherly.