Multi-Packaging-Level Thermal Modeling Technique for Silicon Chip Transistors

Abstract

Although thermal performance is always a critical issue in electronic packaging design at every packaging level, there is a significant lack of reliable and efficient thermal modeling and analysis techniques at the silicon chip level. With millions of transistor gates acting as heat sources, accurate thermal modeling and analysis at micrometer level has not been possible using conventional techniques. For the present study, an efficient and accurate multi-level thermal modeling and analysis technique integrating transistor level into silicon chip level has been developed. The technique combines finite element analysis sub-modeling and superposition methods for more efficient modeling and simulation. Detailed temperature distribution caused by a single heat source is obtained using the finite element sub-modeling technique, while the temperature rise distribution caused by multiple heat sources is obtained using the superposition method. Using the proposed thermal modeling methodology, one case of finite element analysis with a single heat source is sufficient for modeling a silicon chip with millions of transistors acting as heat sources. When the whole package is modeled in the finite element analysis, the effect of the package is also included in the superposition results, which makes possible to model over one million transistors in a silicon chip. No present methodologies for existing silicon chip thermal modeling techniques have been able to model such a large number of transistors. The capabilities of the proposed methodology are demonstrated through a case study involving thermal modeling and analysis of a microprocessor chip.