Abstract
Network-on-Chip (NoC) communication interconnects have emerged as a solution to complex heterogeneous core systems such as those found in Multiprocessor System-on-Chip architectures. Many previous works have used the objectives of power or performance during topology synthesis for regular or application specific based NoC design. However, given the crucial requirements and demands of future on-chip applications, it is imperative that designs consider both power and performance aspects, in addition to other important system constraints. Therefore, in order to address such issues, this thesis work presents a multi-objective Tabu search based topology synthesis technique for designing power and performance efficient Network-on-Chip architectures. The methodology incorporates an analytical and simulation approach in order to compromise between computational time and effort within the algorithm. Furthermore, this work also presents a novel approach for a power and performance tradeoff during contention and deadlock removal within synthesis. The proposed method was tested using seven different multimedia and network benchmark application, where results displayed an increase in performance and decrease in power dissipation in comparison to other previous application specific and regular mesh designs. The analysis method was successful during topology generation, yielding an overall accuracy rate deviation of 19.8% within the worst case scenario.
Highlights
It has become evident that bus-based SoCs which are expected to function at a gigascale level are limited in their ability to efficiently interconnect cores and accommodate the respective communication and energy requirements [1]
This chapter has presented the theory and analysis of the Tabu based topology generation technique proposed in this thesis work
The subsequent chapter will present experimental results obtained by applying this methodology to various benchmark applications
Summary
The System-on-Chip (SoC) design process has been employed to cope with the increasing demands of low power, high-performance, and integration density in deep sub-micron embedded technologies. More advanced SoCs integrate multiple processors when a single processors will not suffice, commonly referred to as Multi-Processor System-on-Chip (MPSoC) architectures. MPSoCs are predominantly used in multimedia and networking communication fields which require large information transmission between cores. It has become evident that bus-based SoCs which are expected to function at a gigascale level are limited in their ability to efficiently interconnect cores and accommodate the respective communication and energy requirements [1]. Bus-based systems can no longer withstand the computational demands of future SoCs, where the Network-on-Chip (NoC) concept has been proposed to overcome such design challenges and meet the various constraints of future SoCs
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