Multilevel process on large area wafers for nanoscale devices

Abstract

Spintronic nanodevices are consolidating a highly reputed position in advanced manufacturing industry, not only due to progresses in magnetic hard disk sensors, but also the memory market. The ability to integrate magnetic thin films on large area wafers and subsequent nanofabrication into functional devices is key for such success. This work describes methodologies used for definition of sub-100 nm pillars, using reliable via opening to contact nanopillars buried in a dielectric film. A two consecutive step electron beam lithography process is used to fabricate current-perpendicular-to plane nanodevices. The first step is required to pattern nanopillars down to 30 nm. The second provides access to nanopillar top through nanovias definition and reactive ion etching. Optimum alignment of multilevel exposures ensures the most accurate positioning in the shortest time. Most importantly, the results are obtained on 150 mm diameter wafers, where additional challenges of uniformity of resists, oxides and metals are critical for end-point control and improved yield of fabricated devices. The design of customized test structures allowed control of etching end-point.