Multilevel logic synthesis technique for efficient verification testing

Abstract

To improve the verification testability of multilevel circuits, a multilevel logic synthesis technique, called VETERAN, for verification testability has been developed. The main steps in VETERAN are first, the determination of the minimum sets of input variables (referred to as 'minimum variable supports') for each output function. Secondly, an efficient verification testing scheme is derived from each set of input variable supports. Thirdly, the minimum variable support and the proper logic (uncomplementary or complementary logic) for every output are determined. Finally, a multilevel circuit, which can be tested by the previously determined verification testing scheme, is implemented by the conventional multilevel logic synthesis techniques. To prove the effectiveness of the proposed technique, it was compared with misII for 59 examples. In all 59 examples, the proposed technique gives results which are better than, or as good, as misII, in terms of testability. For 21 examples, the proposed technique results in smaller circuits, which have a better testability or the same testability.