Multilevel interconnect networks for the end of the roadmap: Conventional Cu/low-k and emerging carbon based interconnects

Abstract

The impact of size effects such as surface and grain boundary scatterings and line edge roughness (LER) on the design of a multi-level interconnection network, and potential power saving offered by individual single-wall nanotube (SWNT) and mono-layer graphene interconnects are investigated and quantified for high-performance and low-cost designs implemented at future technology nodes. It is shown that size effects increase the number of metal levels for a high performance chip by as large as 22.81% and 41.35% at the 21nm and 7.5nm technology nodes, respectively. It has also been demonstrated that individual metallic SWNT and mono-layer graphene interconnects may be used to reduce the interconnect power dissipation in both high-performance and low-cost designs at the end of the roadmap. This is in contrast to previous publications which all indicated that bundles of densely packed SWNTs are needed for interconnect applications.