Multi-level fault simulation of digital systems on decision diagrams

Abstract

A new method for hierarchical fault simulation based on multi-level decision diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-level descriptions for blocks of the RT level structure are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits at these representation levels. The approach proposed allows one to reduce time expenses in the comparison to traditional gate-level fault simulation approach.