Multi-level circuit partitioning for switch-level timing simulation

Abstract

The authors describe two techniques used in switch-level timing simulation. A delay method has been presented which overcomes many drawbacks of existing simulators. The delay method uses voltage-time equations which preserve the nonlinearities of transistors when finding delay values. In addition, a method for processing feedback using multilevel circuit partitioning is suggested as a means of minimizing the amount of block processing during simulation. This method combines the advantages of simple waveform relaxation and dynamic windowing. The multilevel partition can provide a large speedup in runtime for circuits that contain strong feedback loops within weaker feedback loops. The subcircuit block analysis and multilevel partitioning have been implemented in a switch-level timing simulator called IDSIM. IDSIM has consistently run two orders of magnitude faster than SPICE2 with errors less than 10%. >