Multi-layer probe card design with signal/power integrity for wafer-level AP test in LPDDR4 channel

Abstract

In this paper, a vertical probe card consisting of a probe head and a multi-layer ceramic (MLC) board is designed to test wafer-level mobile application processor (AP) chips under LPDDR4 channel specifications. Compared with previously designed probe cards, the newly developed probe card improves signal and power integrity to guarantee the wafer-level AP chips to be operated at 3.2 Gbps speed. In this paper, we propose insertion of ground cobra-shaped needles and ground sheets in the probe head to reduce crosstalk noise and secure return current path. In the far-end crosstalk (FEXT) noise and eye-diagram simulations, FEXT noise in the proposed probe head is suppressed up to 20 dB at 1.6 GHz, and the eye-open size is increased from 18.3 % to 56.6 % at 1.6 Gbps of speed. Measurements are also conducted and well correlated with the simulation results. In MLC board design, ground vias are complemented to near every signal via transitions for improved signal and power integrity. In eye-diagram simulation, eye-opening voltage is enlarged to 65.8 % at 3.2 Gbps. In addition, over 500 of 1 uF decoupling capacitors are implemented on the top layer and the bottom side of the board to lower power distribution network (PDN) impedance. To reduce parasitic inductance on PDN for the memory power supplies, some power planes are repositioned to upper layers of the board. The PDN impedance curves of the memory power domains are lowered by nearly 20 dB above the GHz range. In at-speed test for mobile AP, the designed probe card operates well up to 3.1 Gbps which is the world-wide fastest speed in wafer-level test using a probe card.