Multilayer planarization of polymer dielectrics

Abstract

Polymers are widely used in the microelectronics industry as thin-film interlevel dielectrics layers between metal lines, as passivation layers on semiconductor devices and in various packaging applications. As multiple layers of polymer and patterned metal are constructed, the ability of these polymers to planarize topographical features becomes increasingly important. In this study, the degree of planarization (DOP) for five commercially available polymers has been examined for three different structural configurations with the intent of simulating practical applications. Specifically, this study investigates single layer planarization, multiple coat planarization, and planarization of metal lines patterned on a polymer base. This study also examines the effects of orientation of the metal structure to polymer flow during spin casting and location on the wafer. The polymers are selected to investigate different polymer chemistries frequently used in the microelectronics industry. The underlying structures were fabricated using standard photolithography and electroplating techniques. Feature dimensions include 25-200 /spl mu/m line spacings and widths with the polymer overcoat thickness being twice the height of the underlying structures.