Multilayer Graphene FET Compact Circuit-Level Model With Temperature Effects

Abstract

This paper presents a circuit-level model of a dual-gate bilayer and four-layer graphene field effect transistor. The model provides an accurate estimation of the conductance at the charge neutrality point (CNP). At the CNP, the device has its maximum resistance, at which the model is validated against experimental data of the device off-current for a range of electric fields perpendicular to the channel. The model shows a good agreement for validations carried out at constant and varying temperatures. Using the general Schottky equation, the model estimates the amount of bandgap opening created by the application of an electric field. Also, the model shows good agreement when validated against experiment for the channel output conductance against varying gate voltage for both a bilayer and four-layer graphene channel.