Multilayer Graphene-Based Carbon Interconnect

Abstract

ABSTRACT3D stacked (or uncorrelated) multilayer graphene (s-MLG) is investigated as a potential material platform for carbon-based on-chip interconnects. S-MLG samples are prepared by repeatedly transferring and stacking the large-area CVD-grown graphene monolayers, followed by wire patterning and oxygen plasma etching of graphene. We observed superior wire conduction of s-MLG over that of monolayer graphene or ABAB-stacked multilayer graphene. Further reduction of s-MLG resistivity is anticipated with increasing number of stacked layers. Electrical stress-induced doping technique is used to engineer the Dirac point, as well as to reduce graphene-to-metal contact resistance, improving the overall performance metrics of the s-MLG system. Breakdown experiments show that the current-carrying capacity of s-MLG is significantly enhanced as compared with that of monolayer graphene.