Multi-Fidelity Model-based PLL Design for Enhanced Dynamics and Transient Stability during Fault Ride-Through

Abstract

Reliable grid voltage angle detection by Phase-Locked Loops (PLL) is crucial for grid converter control to accurately inject power and quickly respond to grid faults, e.g., during Fault Ride-Through (FRT). The design of PLLs is typically based on simplified Small-Signal Models (SSMs). However, these models are only valid for small disturbances but inaccurate for severe disturbances. Particularly during grid faults, the grid voltage may exhibit large amplitude steps, phase jumps, and unbalances. Unbalanced faults cause negative sequence components that require PLLs with prefilters. This paper proposes a multi-fidelity model-based design framework for PLLs that utilizes SSMs and Large-Signal Models (LSMs) to optimize phase angle settling times considering the required filter capability. The transient stability boundary of the design parameter space of PLLs can be estimated with the proposed framework, which is exemplarily shown for the Double Synchronous Reference Frame (DSRF)-PLL. Furthermore, we show that the SSM of the DSRF-PLL may predict stable phase angle step responses where the LSM step responses are unstable. Hence, conventional PLL design may lead to unstable PLLs during severe grid faults. The results are verified in simulation and validated in experiments.