Abstract
In a two-stage solid-state transformer (SST) cell, the grid power pulsates at the double-line frequency, yielding second-order harmonic current (SHC) across the unit. SHC into the DC/DC stage causes extra losses in the semiconductors and magnetics, resulting in reduced efficiency and lifetime at the gain of lower DC-link requirement. This paper investigates how the DC-link design affects the SHC distribution using a proposed impedance model, which in turn impacts losses, volume and overall reliability. Particularly, the overall lifetime is evaluated considering the reliability interactions between components resulting from varied DC-link design. The newly introduced reliability dimension provides further insight into the DC-link design, in addition to the voltage ripple requirement and efficiency-power density tradeoff. The model and design concept are verified by the simulation and experiment.
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