Abstract

The enumeration of two-dimensional Costas arrays is a problem with factorial time complexity and has been solved for sizes up to 29 using computer clusters. Costas arrays of higher dimensionality have recently been proposed and their properties are beginning to be understood. This paper presents, to the best of our knowledge, the first proposed implementations for enumerating these multidimensional arrays in GPUs and FPGAs, as well as the first discussion of techniques to prune the search space and reduce enumeration run time. Both GPU and FPGA implementations rely on Costas array symmetries to reduce the search space and perform concurrent explorations over the remaining candidate solutions. The fine grained parallelism utilized to evaluate and progress the exploration, coupled with the additional concurrency provided by the multiple instanced cores, allowed the FPGA (XC5VLX330-2) implementation to achieve speedups of up to 30× over the GPU (GeForce GTX 580).

Highlights

  • A two-dimensional Costas array (2DCA) of size N is a permutation f : N → N such that for every integer h, i, and j, where 1 ≤ h ≤ N −1 and 1 ≤ i, j ≤ N −h, f (i+h)− f (i) = f ( j + h) − f ( j), implies that i = j

  • We focus on the latter kind of multidimensional periodic Costas arrays (MPCAs) due to their richer application range

  • We presented designs for the enumeration of multidimensional periodic Costas arrays in GPUs and FPGAs

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Summary

Introduction

Multidimensional periodic Costas arrays (MPCAs) over elementary Abelian groups, introduced by Moreno and Tirkel , add the property of being periodic over all dimensions. This extends their applicability to digital watermarking of video and combined video and audio, where higher-dimensionality codes are desired [2]. The most common approach for the enumeration of 2DCAs is to use a backtracking algorithm that incorporates symmetries and other observations to further prune the search space. This paper discusses our implementations for the enumeration of (m + 1)-dimensional Costas arrays in GPUs and FPGAs and constitutes the first description of such an enumeration.

Previous Work
Backtracking
GPU Design
FPGA Design
Results and Discussion
Conclusions
Results
Full Text
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