Multicore implementation and performance analysis of a chaos based LSB steganography technique

Abstract

Temporal complexity of data security algorithms for information exchange on internet is becoming a daunting challenge. Performance enhancement of these algorithms using multi core CPUs has now become the standard approach. An OpenMP implementation of chaos based least significant bit steganography technique is proposed in the paper to address this issue. The paper reports (i) standard statistical validation test results viz. histogram analysis, SSIM index, euclidean distance, PSNR for the test sample, (ii) results of the statistical testing on generated chaotic bit sequences, using the NIST suites and (iii) scalability analysis of the multi core implementation of the technique. Significant speed up and linear scalability have been reported with increase in the number of cores from 1 to 16 for Intel Haswell®Processor.