Multichip Module Planarity Requirements Derived From Solder Surface Tension Models

Abstract

Abstract The number of die and routing layers in multichip modules has been steadily increasing, which has exasperated the problem of maintaining module planarity for interconnect to a system board. The usual remedies are to try to balance the composition of the layers on either side of the module's neutral axis or to build the layers on a stiff, planar interposer. Both of these approaches can impact module performance, size and cost. We have examined an alternative approach to accommodating module bow, by allowing the solder ball interconnects to compress or elongate as necessary to maintain electrical connections. This approach is further enhanced by making the module very thin, which does not reduce its bow, but rather allows the high surface tension force exerted by molten solder to flatten the module. We have derived a model for the surface tension force exerted by a solder ball as a function of the degree to which it is compressed or elongated. This model also predicts the maximum elongation that the solder connection can sustain before it ruptures. We have applied this model in a design tool, which allows us to predict the maximum module bow that can be accommodated as a function of the number, size and location of the solder connections and the physical composition of the multichip module.