Multichannel Time-to-Digital Converters With Automatic Calibration in Xilinx Zynq-7000 FPGA Devices

Abstract

This article proposes a weighted histogram calibration method and an automatic calibration architecture to implement high-linearity time-to-digital converters (TDCs) in low-cost Advanced RSIC Machine (ARM)-based system-on-chips (SoCs). The proposed method significantly reduces the nonlinearity introduced by nonuniform bins. It offers automatic calibration without manual interventions using ARM processors. Besides, our design is cost-effective in hardware consumption. We implemented and evaluated a 16-channel TDC system in a low-cost Zynq-7000 ARM-based SoC, in which the programable logic is equivalent to a 28 nm Artix-7 FPGA. The proposed TDC offers a resolution of 9.83 ps with good uniformity, achieving an averaged <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${\rm{DN}}{{\rm{L}}_{{\rm{pk}} - {\rm{pk}}}}$</tex-math></inline-formula> of 0.38 LSB, and an averaged <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${\rm{IN}}{{\rm{L}}_{{\rm{pk}} - {\rm{pk}}}}$</tex-math></inline-formula> of 0.63 LSB.