Multi-Channel FPGA Time-to-Digital Converter With 10 ps Bin and 40 ps FWHM

Davide Portaluppi,Franco Zappa,Iris Cusini,Klaus Pasquinelli

doi:10.1109/tim.2022.3152324

Abstract

We present a novel architecture for multi-channel time-to-digital converters (TDCs) to be implemented into low-cost field-programmable gate arrays (FPGAs), achieving 10-ps least significant bit (LSB), 164- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> full-scale range, and good linearity both in terms of differential nonlinearity (DNL) and integral nonlinearity (INL). The conceived architecture is based on the carry chain delay line model and wave union A method: the positions of both rising and falling edges that propagate in multiple parallel carry chains are recorded each time there is an HIT input. This technique effectively subdivides the ultrawide bins improving the measurement precision and, combined with the sliding-scale technique and continuous code density calibration, improves the TDC linearity. Employing the proposed architecture, we have implemented in a Xilinx Artix-7 FPGA a TDC with 20 timestamp units and validated the device in a time-correlated single photon counting (TCSPC) setup, when connected to an array chip with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times 5$ </tex-math></inline-formula> single-photon avalanche diodes (SPADs).

Highlights

Time-to-Digital Converters (TDCs) are devices able to convert time delays into digital numbers, aiming at high time resolution, precision, conversion speed, and low deadtime
TDCs developed as application-specific integrated circuits (ASICs) can be extremely performing, since they allow the customization of the architecture and the fine tailoring of specific target performance
To provide an equal probability of the HIT input in any position of the clock period, the random START events were generated by a Single Photon Avalanche Diode (SPAD) module, providing a digital pulse for every detected photon originated by a constant light source, while the STOP was generated by the Phase-Locked Loop (PLL) inside the Field Programmable Gate Array (FPGA), in spread spectrum mode, fed by a fixed frequency clock

Summary

INTRODUCTION

Time-to-Digital Converters (TDCs) are devices able to convert time delays into digital numbers, aiming at high time resolution, precision, conversion speed, and low deadtime. TDCs developed as application-specific integrated circuits (ASICs) can be extremely performing, since they allow the customization of the architecture and the fine tailoring of specific target performance They reach single-shot time-jitter precision better than 1 ps [6] and allow the parallelization of many channels [7]. In [13] resolution and precision are instead increased by performing multiple measurements and the conversion linearity is improved by a semi-continuous calibration, while, in [15], the clock skew at the border of the clock regions is exploited to enhance resolution and precision All those approaches add complexity and dead time. We report on the measured performance and linearity improvements achieved thanks to the proposed continuous calibration and bin merging This paragraph of the first footnote will contain the date on which you submitted your paper for review. This paper is organized as follows: Section II describes the TDC architecture and implementation choices; Section III shows the characterization results; Section IV discusses the validation of the multi-channel TDC in a specific application; Section V summarizes the conclusions

TDC ARCHITECTURE

TDC CHARACTERIZATION

EXPERIMENTAL VALIDATION

CONCLUSIONS