Abstract

RSFQ, a Josephson-junction based technology, is becoming attractive due to its low energy and high speed. Researchers have designed cells and built circuits via composition of cells. Some designs have been fabricated and their functionalities and performance verified. This hierarchical approach relies on an abstraction for characterization of cells and composition of cells to design circuits. Researchers have developed such abstractions and methods for characterization of RSFQ cells. However, some instances of cells that are certified as being robust during cell characterization fail when incorporated into circuits. This motivated this research, which we view as the first step in the development of a systematic methodology for verification of cells and circuits in emerging technologies (such as RSFQ) leading to development of more robust abstractions and methods. In this paper, we present a new method for characterization of RSFQ cells to expose a much larger set of vulnerabilities, a systematic approach for identifying the root causes of these vulnerabilities to guide the refinement of cells designs, and a new way to extend test generation approaches to perform design validation at the circuit level. We demonstrate that our new methods and tools expose a large number of vulnerabilities and help identify root causes leading to refined cell designs which almost completely eliminate these vulnerabilities. Finally, we describe our extensions of ATPG for circuit level verification and use it to verify that our refined cells can indeed be composed to create error-free circuits.

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