Multicast schedulers for ATM switches with multiple input queues

Abstract

The evolution of high-speed ATM switches demands the design of efficient, high-performance scheduling algorithms for multicast as well as unicast traffic. Unicast traffic scheduling has improved significantly by adopting the advanced input queuing (virtual output queuing) switch memory architecture. However, conventional multicast scheduling algorithms do not utilize effectively this memory organization and achieve considerably low throughput In this paper, we present two multicast scheduling algorithms, LFINE and MuSe, that employ the advanced input queuing architecture. These algorithms achieve high throughputs by approximating the one provided by FINE introduced in (M. Gamvrili et al., 2003) with a significantly lower implementation cost. In addition they outperform most known alternative multicast scheduling algorithms, such as Tatra and Multicast Greedy. As the results show, both algorithms achieve higher throughput and lower mean packet delay over most alternatives, while providing enhanced characteristics.