Multibranch Inductance Extraction Procedure for Multichip Power Modules

Abstract

This article presents a measurement-based technique for estimating the parasitic inductances associated with the interconnection structures of a multichip power module (MCPM) at a finer granularity than has been previously demonstrated. The technique introduced here makes it possible to determine an estimate of the interconnect inductances at each individual die position within the module geometry. For this purpose, this technique leverages the measured input impedance of an MCPM in the frequency domain, which has been carefully shaped by employing discrete capacitors in place of a semiconductor die. An example of the proposed technique is provided for an MCPM with four die positions per switch position. The provided theoretical formulation is verified by its application to a physical test subject, which is designed to represent a generic MCPM. Owing to the efficiency of this extraction technique and the possibility of providing direct empirical validation for FEA-obtained estimates, the proposed approach is expected to be of particular interest to MCPM designers for use in design optimization.