Abstract
An architecture for a multibit single-stage delta-sigma analog-to-digital converter (ADC) with two-step quantization is presented. Both the most significant bit and least significant bit signals produced by the two-step quantization are fed back simultaneously to all integrator stages, making it suitable for low oversampling ratios. The two-step ADC avoids the problem that the complexity of an internal flash ADC increases exponentially with each added bit. A segmented architecture with coarse/fine dynamic element matching (DEM) and digital-to-analog converter (DAC) is proposed to reduce the complexity of DEM and DAC due to the large internal quantizer. The consequence of the segmentation, mismatch between coarse and fine DACs can be noise shaped by using a digital requantization method. Analysis and behavioral simulation results are presented
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