Multiaccess memory system for attached simd computer

Abstract

In order to reduce the memory access time for a Single-Instruction Multiple-Data stream (SIMD) computer with pq processing elements attached to a host computer, a multiaccess memory system is proposed. The proposed memory system supports simultaneous access to pq data elements within a 4-directional block (p /spl times/ q), a row (1 /spl times/ pq), a column (pq /spl times/ 1), a forward-diagonal, and a backward-diagonal subarray with a constant interval in an arbitrary position in an M /spl times/ N array of data elements, where the number of memory modules, m, is a prime number greater than pq. For the simple and fast address calculation and routing circuit, the address differences between the pq addresses and the base address are arranged in ascending order according to the index numbers of m memory modules from the index number of memory module of the first element. The proposed multiaccess memory system provides more subarray types and more constant intervals than the previous memory systems.